1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In recent years, manufacturing of semiconductor devices in which thin film transistors (hereinafter referred to as TFTs) formed over insulating surfaces of substrates such as glass are utilized as switching elements or the like has been actively pursued. For these thin film transistors, a structure is proposed in which island-shaped semiconductor layers are formed over a substrate having an insulating surface by a CVD method, a photolithography method, or the like, and a part of the island-shaped semiconductor layers is utilized as a channel formation region.
In such a situation, in order to improve characteristics of a thin film transistor, a method for forming a thin film transistor is proposed in which subthreshold swing (here, the subthreshold swing (S value) is referred to as a gate voltage value in a subthreshold region while a drain current changes by one digit while a drain voltage is constant) is lowered by reducing the thickness of a semiconductor layer. However, there have been problems such that the resistance of each of a source region and a drain region and the contact resistance are increased by reducing the thickness of the semiconductor layer, which leads to a decrease in the on-state current.
In order to solve these problems, a thin film transistor formed using a semiconductor layer in which the thickness of a channel formation region is smaller than the thickness of a source region or a drain region is proposed (e.g., Patent Document 1: Japanese Published Patent Application No. S61-48975, Patent Document 2: Japanese Published Patent Application No. H5-110099, and Non-Patent Document 1: Electrochemical Society Proceedings Volume 98-22, PP. 204-220). For example, Patent Document 1 discloses a method for forming a thin film transistor in which a semiconductor layer is formed on a flat surface of an insulating substrate and the channel formation region is locally thinned by performing selective etching. Patent Document 2 discloses a method in which a semiconductor layer is formed over an insulating substrate provided with a protrusion in a portion corresponding to a channel formation region and an upper surface of the semiconductor layer formed over the protrusion is etched so that the semiconductor layer is planarized to thin the channel formation region. Non-Patent Document 1 discloses a method for manufacturing a thin film transistor in which a part of an n+Si film is dry etched after the n+Si film is deposited over a p−Si film. In this method, a portion where the p−Si film and the n+Si film are stacked is used as a source region or a drain region, and the p−Si film under the etched n+Si film is used as a channel formation region.
However, as described in Patent Document 1, there is a problem in that the fabrication process is unstable because the formation of a semiconductor layer having different thicknesses on a flat surface of an insulating substrate requires selective etching of the semiconductor layer to form a channel formation region with a desired thickness. In the method described in Patent Document 2, there is a problem in that the number of steps is increased because etching treatment is performed in order to planarize the surface of a semiconductor layer and a process is unstable because selective etching treatment of the semiconductor layer is required to form the semiconductor layer with a planarized surface. In the method described in Non-Patent Document 1, etching is necessary after an Si film is deposited twice, and hence the number of steps is increased. In particular, in the case where an n-channel transistor and a p-channel transistor are formed, the number of depositions of Si films and the number of etching processes are increased further. In addition, there is a problem in that a process is unstable because well-controlled etching treatment of the Si film is required. Particularly, it is quite difficult to control the thickness of the semiconductor layer in an attempt to fabricate the channel formation region with a thickness of 50 nm or less.